The present invention relates to semiconductor memory devices, and more particularly relates to technology that is effectively applicable to a nonvolatile semiconductor memory device, in which resistance change devices are used, and the like.
In recent years, in semiconductor integrated circuit technology, microscaling of fabrication processes has progressed, such that gate oxide films have become thinner and gate electrode materials and the like have been improved. Flash memories, EEPROMs, and other rewritable devices have also achieved technical progress, such as larger scale and higher levels of integration. In the field of systems using semiconductor devices, the intended uses of the devices required therein have been changing; in some cases, devices for security purposes, nonvolatile memory devices, such as IC tags, and OTP devices are included, and there has been an increasing tendency to include rewritable large-capacity nonvolatile memories. Recently, new nonvolatile memories achieving further reduction in area have come along as typical FG nonvolatile memories, such as flash memories and EEPROMs, and have been attracting attention. Representative examples of those memories include FeRAMs using ferroelectric substance, MRAMs using magnetism, and PRAMs as phase change memories, resistance change memories, and various other types of memories.
Of the new nonvolatile memories described above, the resistance change memory devices include an oxide film made of material having a perovskite structure or material such as binary system transition metal oxide. The resistance value of such a memory device is set to a high resistance value (during a set operation) or is set to a low resistance value (during an erasing or reset operation) to make the memory device perform nonvolatile storage.
Conventional voltage bias conditions during set and reset operations in such a resistance change memory have been to use positive and negative voltages. For example, as a bias voltage applied across both ends of a resistance change memory device, a positive voltage having a given value is used, e.g., at the time of writing, and a negative voltage having a give value, whose absolute number is the same as that of the positive voltage but whose sign is different from that of the positive voltage, is used at the time of erasing. Also, the values of the positive and negative voltages vary widely from about 1V to about 5V. This kind of technology has been described in Japanese Laid-Open Publication No. 2004-158119, for example.
However, the conventional resistance change memory described above has the following problem, because the positive and negative voltages are used as the bias voltages.
FIG. 2 shows states in which bias voltages are applied at the time of data writing (set and rest operations) in a conventional semiconductor memory device.
In FIG. 2, the reference numeral 203 refers to a resistance change memory device; 201 to one terminal of the resistance change memory device 203; 202 to the other terminal of the resistance change memory device 203; 204 to a state in which a set bias voltage is applied at the time of a set operation in the resistance change memory device 203, and 205 to a state in which a reset bias voltage is applied at the time of a reset operation in the resistance change memory device 203.
The following can be seen from FIG. 2. The following description is based on the assumption that, in the resistance change memory device 203, a potential difference between the two terminals 201 and 202 required when a set operation for writing data and a reset operation for the written data are performed is a set value Vd. With the other terminal 202 being always at the ground potential GND, the one terminal 201 is subjected to the application of the positive set value +Vd at the time of the set operation, and subjected to the application of the negative set value −Vd at the time of the reset operation, such that the potential of the terminal 201 makes transition between the positive voltage +Vd and the negative voltage −Vd. In this case, since the amount of voltage transition of the terminal 201 is 2×Vd, the large amplitude difference is necessary and a negative potential generation circuit for generating the negative set value −Vd is also needed. However, in an actual semiconductor device having a twin-well structure or the like, a negative potential should not be generated, and it is thus difficult to employ this technology.
Therefore, as a structure in which no negative potential generation circuits are needed, the voltage of the fixed-potential terminal 202 may be set to the positive voltage +Vd, for example. In that case, nevertheless, two voltages, i.e., a boosted voltage of 2×Vd and the ground voltage GND, will be necessary for the one terminal 201, and the voltage amplitude of the terminal 201 will be still as large as 2×Vd, which is the same as the amplitude required in the above-described case. Furthermore, even if the potential is produced internally, the current-supplying capability of the boosted-potential generation circuit is likely to be low, thereby causing drawbacks, such as limitation on the number of bits at the time of writing.